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Renesas Electronics /R7FA6M3AH /GLCDC /GR1_FLM3

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Interpret as GR1_FLM3

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LNOFF

Description

Graphics 1 Frame Buffer Control Register 3

Fields

LNOFF

Macro line offset address for accessing graphics data(frame buffer data)Signed; 16-bit integer

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data